The MPC755 is targeted for low-cost, low-power systems and supports the following power management features—doze, nap, sleep, and dynamic power management. The MPC755 consists of a processor core and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support the L2 cache interface.

Branch processing unit

— Four instructions fetched per clock

— One branch processed per cycle (plus resolving two speculations)

— Up to one speculative stream in execution, one additional speculative stream in fetch

— 512-entry branch history table (BHT) for dynamic prediction

— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating

branch delay slots

Dispatch unit

— Full hardware detection of dependencies (resolved in the execution units)

— Dispatch two instructions to six independent units (system, branch, load/store, fixed-point

unit 1, fixed-point unit 2, floating-point)

— Serialization control (predispatch, postdispatch, execution serialization)

Decode

— Register file access

— Forwarding control

— Partial instruction decode

Completion

— Six-entry completion buffer

— Instruction tracking and peak completion of two instructions per cycle

— Completion of instructions in program order while supporting out-of-order instruction

execution, completion serialization, and all instruction flow changes

Fixed point units (FXUs) that share 32 GPRs for integer operands

— Fixed Point Unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

— Fixed Point Unit 2 (FXU2)—shift, rotate, arithmetic, logical

— Single-cycle arithmetic, shifts, rotates, logical

— Multiply and divide support (multi-cycle)

— Early out multiply